Evaluating Network Processors in IP Forwarding

This paper evaluates the performance of emerging network processors—in particular, designs that employ multiple hardware contexts to hide memory latency— in constructing IP routers. Such processors are designed to forward minimum-sized IP packets at line speeds, with the advantage (over ASIC-based solutions) of being programmable. However, programming such network processors involves two challenges. The first is how to effectively employ the multiple contexts in a way that fully utilizes the memory bandwidth. The second is how to allow the network processor to be programmed dynamically (so it can support new functionality) without violating the processor’s tight timing constraints. This paper addresses both of these challenges on a prototype board that uses the IXP1200 network processor. We demonstrate that it is possible to support 8 100Mbps ports with enough headroom to access up to 224 bytes of state information for each minimum-sized IP packet.